Design of Low Power Multiplier with Reduced Spurious Transition Activity Technique for Efficient Neural Network

This paper explores the implementation approaches of a low power Modified Booth Multiplier (MBM) with Reduced Spurious Transition Activity Technique (RSTAT) and its application on a low power (LP) neural network. This RSTAT approach has been applied on both the compression tree of multipliers and the modified Booth Encoder to enlarge the power clampdown, for high speed and low power purposes. To filter out the spurious switching power of the multiplier, there are two approaches, one is using registers and using AND gates, to assert the data signals of LP multipliers after the data transition has been proposed. The RSTAT approach leads to a 40% power consumption reduction and speed improvement when compared with the other power minimization technique. An artificial neural network is a system consisting of small processing units (called neurons) that perform specific tasks in parallel. The hardware implementation of such neural network will mainly consist of a multiplier circuit for the product term along with an adder circuit for the summation. The above low power multiplier can be used in the neural network for low power VLSI implementations.